X-NAND
Future Architecture of 3D NAND
QLC 3D NAND flash has already found many applications due to its higher density and lower price than other NAND types. However, a serious limitation is that QLC has relatively low performance, especially write speed. NEO Semiconductor has developed a new architecture called X-NAND, which can increase QLC NAND's random read/write speed by 3X and sequential read/write throughput by 15-30X. That results in QLC NAND with read/write performance comparable to SLC NAND. X-NAND architecture can produce the high-speed, low-cost solution required by such emerging applications as AI, 5G, real-time analysis, VR/AR, and cybersecurity. X-NAND architecture can be applied to SLC to PLC flash. The architecture enables NAND flash to be readily integrated into ultra-high-bandwidth 3D integrated chips.
X-NAND (trademark pending) is the property of NEO Semiconductor, Inc.
Single Buffer/Multiple Bit Line Operation
X-NAND architecture allows one page buffer to perform read and write operations to 16 or more bit lines. This increases the number of planes in Y-direction to 16 times or more without increasing the number of total page buffers. As a result, the read and write data throughputs are increased by 16 times. In addition, because the bit line length and capacitance are reduced to 1/16, the random read speed and program-verification speed are drastically increased. The bit line power consumption is also reduced to 1/16.
SLC/QLC Parallel Programming
X-NAND’s unique SLC/QLC Parallel Programming allows the data to be programmed to QLC pages in SLC speed for the entire memory capacity. This solves the conventional NAND’s SLC cache full problem. When the conventional SLC cache is full, the data will be directly written to QLC cells and the speed will be dropped to about only 10%. X-NAND solves this problem and provides an excellent solution for heavy-write systems such as data centers and NAS.
No SLC Cache Full Problem
X-NAND’s unique SLC/QLC Parallel Programming allows the data to be programmed to QLC pages in SLC speed for the entire memory capacity. This solves the conventional NAND’s SLC cache full problem. When the conventional SLC cache is full, the data will be directly written to QLC cells and the speed will be dropped to about only 10%. X-NAND solves this problem and provides an excellent solution for heavy-write systems such as data centers and NAS.
1/16 Bit Line Power Consumption
X-NAND’s bit line capacitance is only 1/16 of the conventional NAND’s. Therefore, the bit line’s power consumption for read and write operations can be reduced to only 1/16. This drastically increases the battery life for smartphones, handheld, and IoT devices.
16X Parallelism Per Chip
X-NAND’s 16-plane architecture provides high parallelism in chip level. Compared with the conventional NAND using 2 - 4 planes, one X-NAND chip can provide the same parallelism of 4 - 8 NAND chips. This allows small form-factor such as M.2 and eMMC to have the similar performance of large systems with smaller footprint.
Flash Memory Summit 2020
Nov. 10-12, 2020
We are presenting X-NAND architecture in Flash Memory Summit 2020, Keynote 11. Please come and join us !